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Proceedings Paper

Recent progress on multipatterning: approach to pattern placement correction
Author(s): Hidetami Yaegashi; Kenichi Oyama; Arisa Hara; Sakurako Natori; Shohei Yamauchi; Masatoshi Yamato; Noriaki Okabe; Kyohei Koike
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Paper Abstract

Multi-patterning technology using 193nm immersion lithography has been used since the 22nm logic node generation and it appears that it will continue to be used as far as the 14nm generation. At the same time, the industry trend is to simplify pattern design and reduce complexity in lithography though single directional (1D) layout[1]. On the other hand, there is increasing concern about pattern placement error in the application of this technology. This paper focuses on pattern placement variation in the process steps of pattern formation in 1D layout design, presents the results of a study on the effects of factors other than overlay accuracy on microscopic behavior, and describes techniques for improving pattern placement.

Paper Details

Date Published: 20 March 2015
PDF: 11 pages
Proc. SPIE 9425, Advances in Patterning Materials and Processes XXXII, 942502 (20 March 2015); doi: 10.1117/12.2087003
Show Author Affiliations
Hidetami Yaegashi, Tokyo Electron Ltd. (Japan)
Kenichi Oyama, Tokyo Electron Ltd. (Japan)
Arisa Hara, Tokyo Electron Ltd. (Japan)
Sakurako Natori, Tokyo Electron Ltd. (Japan)
Shohei Yamauchi, Tokyo Electron Ltd. (Japan)
Masatoshi Yamato, Tokyo Electron Ltd. (Japan)
Noriaki Okabe, Tokyo Electron Ltd. (Japan)
Kyohei Koike, Tokyo Electron Ltd. (Japan)


Published in SPIE Proceedings Vol. 9425:
Advances in Patterning Materials and Processes XXXII
Thomas I. Wallow; Christoph K. Hohle, Editor(s)

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