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Proceedings Paper

A methodology to optimize design pattern context size for higher sensitivity to hotspot detection using pattern association tree (PAT)
Author(s): Shikha Somani; Piyush Pathak; Piyush Verma; Sriram Madhavan; Luigi Capodieci
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Paper Abstract

Pattern based design rule checks have emerged as an alternative to the traditional rule based design rule checks in the VLSI verification flow [1]. Typically, the design-process weak-points, also referred as design hotspots, are classified into patterns of fixed size. The size of the pattern defines the radius of influence for the process. These fixed sized patterns are used to search and detect process weak points in new designs without running computationally expensive process simulations. However, both the complexity of the pattern and different kinds of physical processes affect the radii of influence. Therefore, there is a need to determine the optimal pattern radius (size) for efficient hotspot detection. The methodology described here uses a combination of pattern classification and pattern search techniques to create a directed graph, referred to as the Pattern Association Tree (PAT). The pattern association tree is then filtered based on the relevance, sensitivity and context area of each pattern node. The critical patterns are identified by traversing the tree and ranking the patterns. This method has plausible applications in various areas such as process characterization, physical design verification and physical design optimization. Our initial experiments in the area of physical design verification confirm that a pattern deck with the radius optimized for each pattern is significantly more accurate at predicting design hotspots when compared to a conventional deck of fixed sized patterns.

Paper Details

Date Published: 18 March 2015
PDF: 13 pages
Proc. SPIE 9427, Design-Process-Technology Co-optimization for Manufacturability IX, 94270T (18 March 2015); doi: 10.1117/12.2086954
Show Author Affiliations
Shikha Somani, GLOBALFOUNDRIES Inc. (United States)
Piyush Pathak, GLOBALFOUNDRIES Inc. (United States)
Piyush Verma, GLOBALFOUNDRIES Inc. (United States)
Sriram Madhavan, GLOBALFOUNDRIES Inc. (United States)
Luigi Capodieci, GLOBALFOUNDRIES Inc. (United States)

Published in SPIE Proceedings Vol. 9427:
Design-Process-Technology Co-optimization for Manufacturability IX
John L. Sturtevant; Luigi Capodieci, Editor(s)

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