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Proceedings Paper

An efficient auto TPT stitch guidance generation for optimized standard cell design
Author(s): Nagaraj Chary Samboju; Soo-Han Choi; Srini Arikati; Erdem Cilingir
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Paper Abstract

As the technology continues to shrink below 14nm, triple patterning lithography (TPT) is a worthwhile lithography methodology for printing dense layers such as Metal1. However, this increases the complexity of standard cell design, as it is very difficult to develop a TPT compliant layout without compromising on the area. Hence, this emphasizes the importance to have an accurate stitch generation methodology to meet the standard cell area requirement as defined by the technology shrink factor. In this paper, we present an efficient auto TPT stitch guidance generation technique for optimized standard cell design. The basic idea here is to first identify the conflicting polygons based on the Fix Guidance [1] solution developed by Synopsys. Fix Guidance is a reduced sub-graph containing minimum set of edges along with the connecting polygons; by eliminating these edges in a design 3-color conflicts can be resolved. Once the conflicting polygons are identified using this method, they are categorized into four types [2] - (Type 1 to 4). The categorization is based on number of interactions a polygon has with the coloring links and the triangle loops of fix guidance. For each type a certain criteria for keep-out region is defined, based on which the final stitch guidance locations are generated. This technique provides various possible stitch locations to the user and helps the user to select the best stitch location considering both design flexibility (max. pin access/small area) and process-preferences. Based on this technique, a standard cell library for place and route (P and R) can be developed with colorless data and a stitch marker defined by designer using our proposed method. After P and R, the full chip (block) would contain the colorless data and standard cell stitch markers only. These stitch markers are considered as “must be stitch” candidates. Hence during full chip decomposition it is not required to generate and select the stitch markers again for the complete data; therefore, the proposed method reduces the decomposition time significantly.

Paper Details

Date Published: 18 March 2015
PDF: 12 pages
Proc. SPIE 9427, Design-Process-Technology Co-optimization for Manufacturability IX, 94270A (18 March 2015); doi: 10.1117/12.2085834
Show Author Affiliations
Nagaraj Chary Samboju, Synopsys India Pvt. Ltd. (India)
Soo-Han Choi, Synopsys, Inc. (United States)
Srini Arikati, Synopsys, Inc. (United States)
Erdem Cilingir, Synopsys, Inc. (United States)


Published in SPIE Proceedings Vol. 9427:
Design-Process-Technology Co-optimization for Manufacturability IX
John L. Sturtevant; Luigi Capodieci, Editor(s)

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