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Sustainability and applicability of spacer-related patterning towards 7nm node
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Paper Abstract

Self-aligned multiple patterning technique has enabled the further down scaling through 193 immersion lithography extension [1-5]. In particular, focus on the logic device scaling, we have finished the verification of patterning technology of up to 10nm node [6-7], we will discuss about some patterning technologies that are required to 7nm node. For critical layers in FinFET devices that presume a 1D cell design, there is also a need not just for the scaling of grating patterns but also for pattern cutting process. In 7nm node, cutting number increase in metal or fin layer, and also pattern splitting of contact or via is complicated, so both cost reduction and process controllability including EPE are strongly required. For example, inverse hardmask scheme in metal layer can improve CD variation of the Cu wiring. Furthermore hole pattern shrink technology in contact layer, by the combination with the exposure technique which has k1 0.25 or less, can achieve both cost reduction and reducing the numbers of pitch splitting. This paper presents the possibility of immersion-based multiple patterning techniques for up to 7nm node.

Paper Details

Date Published: 20 March 2015
PDF: 10 pages
Proc. SPIE 9425, Advances in Patterning Materials and Processes XXXII, 942514 (20 March 2015); doi: 10.1117/12.2085730
Show Author Affiliations
Kenichi Oyama, Tokyo Electron Ltd. (Japan)
Shohei Yamauchi, Tokyo Electron Ltd. (Japan)
Arisa Hara, Tokyo Electron Ltd. (Japan)
Sakurako Natori, Tokyo Electron Ltd. (Japan)
Masatoshi Yamato, Tokyo Electron Ltd. (Japan)
Noriaki Okabe, Tokyo Electron Ltd. (Japan)
Kyohei Koike, Tokyo Electron Ltd. (Japan)
Hidetami Yaegashi, Tokyo Electron Ltd. (Japan)

Published in SPIE Proceedings Vol. 9425:
Advances in Patterning Materials and Processes XXXII
Thomas I. Wallow; Christoph K. Hohle, Editor(s)

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