Share Email Print
cover

Proceedings Paper

20nm CMP model calibration with optimized metrology data and CMP model applications
Author(s): Ushasree Katakamsetty; Dinesh Koli; Sky Yeo; Colin Hui; Ruben G. Ghulghazaryan; Burak Aytuna; Jeff Wilson
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Chemical Mechanical Polishing (CMP) is the essential process for planarization of wafer surface in semiconductor manufacturing. CMP process helps to produce smaller ICs with more electronic circuits improving chip speed and performance. CMP also helps to increase throughput and yield, which results in reduction of IC manufacturer’s total production costs. CMP simulation model will help to early predict CMP manufacturing hotspots and minimize the CMP and CMP induced Lithography and Etch defects [2]. In the advanced process nodes, conventional dummy fill insertion for uniform density is not able to address all the CMP short-range, long-range, multi-layer stacking and other effects like pad conditioning, slurry selectivity, etc. In this paper, we present the flow for 20nm CMP modeling using Mentor Graphics CMP modeling tools to build a multilayer Cu-CMP model and study hotspots. We present the inputs required for good CMP model calibration, challenges faced with metrology collections and techniques to optimize the wafer cost. We showcase the CMP model validation results and the model applications to predict multilayer topography accumulation affects for hotspot detection. We provide the flow for early detection of CMP hotspots with Calibre CMPAnalyzer to improve Design-for-Manufacturability (DFM) robustness.

Paper Details

Date Published: 18 March 2015
PDF: 9 pages
Proc. SPIE 9427, Design-Process-Technology Co-optimization for Manufacturability IX, 94270U (18 March 2015); doi: 10.1117/12.2085728
Show Author Affiliations
Ushasree Katakamsetty, GLOBALFOUNDRIES, Inc. (Singapore)
Dinesh Koli, GLOBALFOUNDRIES Inc. (United States)
Sky Yeo, GLOBALFOUNDRIES Singapore (Singapore)
Colin Hui, GLOBALFOUNDRIES, Inc. (Singapore)
Ruben G. Ghulghazaryan, Mentor Graphics Corp. (Armenia)
Burak Aytuna, Mentor Graphics Corp. (United States)
Jeff Wilson, Mentor Graphics Corp. (United States)


Published in SPIE Proceedings Vol. 9427:
Design-Process-Technology Co-optimization for Manufacturability IX
John L. Sturtevant; Luigi Capodieci, Editor(s)

© SPIE. Terms of Use
Back to Top