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Proceedings Paper

Directed self-assembly lithography using coordinated line epitaxy (COOL) process
Author(s): Yuriko Seino; Yusuke Kasahara; Hironobu Sato; Katsutoshi Kobayashi; Hitoshi Kubota; Shinya Minegishi; Ken Miyagi; Hideki Kanai; Katsuyoshi Kodera; Naoko Kihara; Yoshiaki Kawamonzen; Toshikatsu Tobana; Masayuki Shiraishi; Satoshi Nomura; Tsukasa Azuma
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Paper Abstract

In this study, half-pitch (HP) 15 nm line-and-space (L/S) metal wires were successfully fabricated and fully integrated on a 300 mm wafer by applying directed self-assembly (DSA) lithography and pattern transfer for semiconductor device manufacturing. In order to evaluate process performances of DSA, we developed a simple sub-15 nm L/S patterning process using polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) lamellar block copolymer (BCP), which utilizes trimming resist and shallow etching spin-on-glass (SOG) as pinning guide[1]-[4]. From the results of defect inspection after SOG etch using Electron Beam (EB) inspection system, defects were classified as typical DSA defects or defects relating to DSA pattern transfer. From the evaluation of DSA L/S pattern Critical Dimension (CD), roughness and local placement error using CD-SEM, it is considered that isolated PS lines are placed at the centerline between guides and that placement of paired PS lines depends on the guide width. The control of the guide resist CD is the key to local placement error and the paired lines adjacent to the guide shifted toward the outside (0.5 nm) along the centerline of the isolated line after SOG etch. We demonstrated fabrication of HP 15 nm metal wires in trenches formed by the DSA process with reactive ion etching (RIE), followed by metal chemical vapor deposition (CVD) and chemical mechanical polishing (CMP). By SEM observation of alignment errors between the trenches and connect spaces, overlay shift patterns (-4 nm) in guide lithography mask were fabricated without intra-wafer alignment errors.

Paper Details

Date Published: 19 March 2015
PDF: 7 pages
Proc. SPIE 9423, Alternative Lithographic Technologies VII, 942316 (19 March 2015); doi: 10.1117/12.2085697
Show Author Affiliations
Yuriko Seino, EUVL Infrastructure Development Ctr., Inc. (Japan)
Yusuke Kasahara, EUVL Infrastructure Development Ctr., Inc. (Japan)
Hironobu Sato, EUVL Infrastructure Development Ctr., Inc. (Japan)
Katsutoshi Kobayashi, EUVL Infrastructure Development Ctr., Inc. (Japan)
Hitoshi Kubota, EUVL Infrastructure Development Ctr., Inc. (Japan)
Shinya Minegishi, EUVL Infrastructure Development Ctr., Inc. (Japan)
Ken Miyagi, EUVL Infrastructure Development Ctr., Inc. (Japan)
Hideki Kanai, EUVL Infrastructure Development Ctr., Inc. (Japan)
Katsuyoshi Kodera, EUVL Infrastructure Development Ctr., Inc. (Japan)
Naoko Kihara, EUVL Infrastructure Development Ctr., Inc. (Japan)
Yoshiaki Kawamonzen, EUVL Infrastructure Development Ctr., Inc. (Japan)
Toshikatsu Tobana, EUVL Infrastructure Development Ctr., Inc. (Japan)
Masayuki Shiraishi, EUVL Infrastructure Development Ctr., Inc. (Japan)
Satoshi Nomura, EUVL Infrastructure Development Ctr., Inc. (Japan)
Tsukasa Azuma, EUVL Infrastructure Development Ctr., Inc. (Japan)


Published in SPIE Proceedings Vol. 9423:
Alternative Lithographic Technologies VII
Douglas J. Resnick; Christopher Bencher, Editor(s)

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