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Proceedings Paper

New VLSI architecture for full-search vector quantization
Author(s): Chin-Liang Wang; Ker-Min Chen
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Paper Abstract

This paper presents a new systolic architecture to realize the encoder of the full-search vector quantization (VQ) for high-speed applications. The architecture possesses the features of regularity and modularity, and is thus very suitable for VLSI implementation. For a codebook of size N and dimension k, the VQ encoder has area complexity of O(N), time complexity of O(k), and I/O bandwidth of O(k). It reaches a compromise between hardware cost and speed requirement as compared to existing systolic/regular VQ encoders. At the current state of VLSI technology, the proposed system can easily be realized in a single chip for most practical applications. In addition, it provides flexibility in changing the codebook contents and extending the codebook size, where the latter is achieved simply by cascading some identical basic chips. With 0.8 micrometers CMOS technology to implement the proposed VQ encoder for N equals 256 and k equals 16, the die size required is about 5 X 8.5 mm2 and the processing speed is up to 100 M samples per second. These features show that the proposed architecture is attractive for use in high-speed image/video applications.

Paper Details

Date Published: 21 April 1995
PDF: 10 pages
Proc. SPIE 2501, Visual Communications and Image Processing '95, (21 April 1995); doi: 10.1117/12.206757
Show Author Affiliations
Chin-Liang Wang, National Tsing Hua Univ. (Taiwan)
Ker-Min Chen, National Tsing Hua Univ. (Taiwan)


Published in SPIE Proceedings Vol. 2501:
Visual Communications and Image Processing '95
Lance T. Wu, Editor(s)

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