Share Email Print

Proceedings Paper

Design of a dataway processor for a parallel image signal processing system
Author(s): Mitsuru Nomura; Tetsuro Fujii; Sadayasu Ono
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Recently, demands for high-speed signal processing have been increasing especially in the field of image data compression, computer graphics, and medical imaging. To achieve sufficient power for real-time image processing, we have been developing parallel signal-processing systems. This paper describes a communication processor called 'dataway processor' designed for a new scalable parallel signal-processing system. The processor has six high-speed communication links (Dataways), a data-packet routing controller, a RISC CORE, and a DMA controller. Each communication link operates at 8-bit parallel in a full duplex mode at 50 MHz. Moreover, data routing, DMA, and CORE operations are processed in parallel. Therefore, sufficient throughput is available for high-speed digital video signals. The processor is designed in a top- down fashion using a CAD system called 'PARTHENON.' The hardware is fabricated using 0.5-micrometers CMOS technology, and its hardware is about 200 K gates.

Paper Details

Date Published: 21 April 1995
PDF: 11 pages
Proc. SPIE 2501, Visual Communications and Image Processing '95, (21 April 1995); doi: 10.1117/12.206741
Show Author Affiliations
Mitsuru Nomura, NTT Optical Network Systems Labs. (Japan)
Tetsuro Fujii, NTT Optical Network Systems Labs. (Japan)
Sadayasu Ono, NTT Optical Network Systems Labs. (Japan)

Published in SPIE Proceedings Vol. 2501:
Visual Communications and Image Processing '95
Lance T. Wu, Editor(s)

© SPIE. Terms of Use
Back to Top