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Proceedings Paper

The analysis and design of high speed double delta sampling circuit for CMOS image sensor
Author(s): Xiaohui Liu; Yuanfu Zhao; Liyan Liu; Chunfang Wang; Xiaofeng Jin; Yue Zhao
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Paper Abstract

A high-speed double delta sampling (DDS) circuit with pipelined structure for CMOS image sensor (CIS) is presented. Considering the low readout speed of the DDS circuit compare with correcting double sampling (CDS) circuit, We separate the main operation of DDS circuit into two steps, and run the two steps alternately in odd readout column and even readout column, which seems like the pipelined operation. Thus, the readout speed of the DDS will as twice as fast than the traditional DDS. The architecture and readout sequence of the new circuit are introduced in detail. Meanwhile simulation results indicate the proposed circuit can achieve a high speed performance.

Paper Details

Date Published: 16 April 2014
PDF: 5 pages
Proc. SPIE 9159, Sixth International Conference on Digital Image Processing (ICDIP 2014), 91590P (16 April 2014); doi: 10.1117/12.2064181
Show Author Affiliations
Xiaohui Liu, Beijing Microelectronic Technology Institute (China)
Yuanfu Zhao, Beijing Microelectronic Technology Institute (China)
Liyan Liu, Beijing Microelectronic Technology Institute (China)
Chunfang Wang, Beijing Microelectronic Technology Institute (China)
Xiaofeng Jin, Beijing Microelectronic Technology Institute (China)
Yue Zhao, Beijing Microelectronic Technology Institute (China)


Published in SPIE Proceedings Vol. 9159:
Sixth International Conference on Digital Image Processing (ICDIP 2014)
Charles M. Falco; Chin-Chen Chang; Xudong Jiang, Editor(s)

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