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Proceedings Paper

Mk x Nk gated CMOS imager
Author(s): James Janesick; Tom Elliott; James Andrews; John Tower; Perry Bell; Alan Teruya; Joe Kimbrough; Jeanne Bishop
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Paper Abstract

Our paper will describe a recently designed Mk x Nk x 10 um pixel CMOS gated imager intended to be first employed at the LLNL National Ignition Facility (NIF). Fabrication involves stitching MxN 1024x1024x10 um pixel blocks together into a monolithic imager (where M = 1, 2, . .10 and N = 1, 2, . . 10). The imager has been designed for either NMOS or PMOS pixel fabrication using a base 0.18 um/3.3V CMOS process. Details behind the design are discussed with emphasis on a custom global reset feature which erases the imager of unwanted charge in ~1 us during the fusion ignition process followed by an exposure to obtain useful data. Performance data generated by prototype imagers designed similar to the Mk x Nk sensor is presented.

Paper Details

Date Published: 10 September 2014
PDF: 13 pages
Proc. SPIE 9211, Target Diagnostics Physics and Engineering for Inertial Confinement Fusion III, 921106 (10 September 2014); doi: 10.1117/12.2063524
Show Author Affiliations
James Janesick, SRI-Sarnoff (United States)
Tom Elliott, SRI-Sarnoff (United States)
James Andrews, SRI-Sarnoff (United States)
John Tower, SRI-Sarnoff (United States)
Perry Bell, Lawrence Livermore National Lab. (United States)
Alan Teruya, Lawrence Livermore National Lab. (United States)
Joe Kimbrough, Lawrence Livermore National Lab. (United States)
Jeanne Bishop, Chronicle Technology Inc. (United States)


Published in SPIE Proceedings Vol. 9211:
Target Diagnostics Physics and Engineering for Inertial Confinement Fusion III
Perry M. Bell; Gary P. Grim, Editor(s)

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