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Proceedings Paper

Optoelectronic interconnect architecture of parallel modified signed-digit adder and subtractor
Author(s): DeGui Sun; Na-Xin Wang; Li-Ming He; Zhao-Heng Weng; Daheng Wang; Ray T. Chen
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Paper Abstract

In this paper, a space-position-logic-encoding scheme is proposed, which not only makes best use of the convenience of binary logic operation, but is also suitable for the trinary property of modified signed-digit numbers. Based on the space-position-logic-encoding scheme, a fully parallel modified signed-digit adder and subtracter is built by use of optoelectronic switch and microstructure interconnect technologies. Thus an effective combination of a parallel algorithm and a parallel architecture is implemented. Finally, both simulation results and experimental results are provided.

Paper Details

Date Published: 5 April 1995
PDF: 9 pages
Proc. SPIE 2400, Optoelectronic Interconnects III, (5 April 1995); doi: 10.1117/12.206328
Show Author Affiliations
DeGui Sun, Univ. of Texas/Austin (Canada)
Na-Xin Wang, Changchun Institute of Optics and Fine Mechanics (China)
Li-Ming He, Changchun Institute of Optics and Fine Mechanics (China)
Zhao-Heng Weng, Changchun Institute of Optics and Fine Mechanics (China)
Daheng Wang, Changchun Institute of Optics and Fine Mechanics (China)
Ray T. Chen, Univ. of Texas/Austin (United States)


Published in SPIE Proceedings Vol. 2400:
Optoelectronic Interconnects III
Ray T. Chen; Harvard Scott Hinton, Editor(s)

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