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Proceedings Paper

Status and outlook of STT-MRAM development
Author(s): T. Min; G. S. Kar; J. Swerts; S. Mertens; S. Coseman; J. Bekaert; K. Xu; L. Souriau; D. Radisic; H. Okuyama; K. Nishimura; T. Seino; K. Tsunekawa
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Paper Abstract

MTJ stack is optimized for TMR at low RA region, high PMA and 400oC post annealing capability. Atomic level smooth bottom electrode with 0.5A roughness was developed and positive effects on annealing capability and PMA was demonstrated. The scaling challenge of STT-MRAM read operation down to sub-10nm is discussed. Various contributing factors to the MTJ cell resistance variation were investigated with focus on MRAM cell variation due to advanced lithography patterning techniques. With SADP or DSA, the MRAM cell size can be scaled down to 18nm physical dimension with 4.2% σ/μ cell area variation, good enough for sub-10nm technology node.

Paper Details

Date Published: 28 August 2014
PDF: 8 pages
Proc. SPIE 9167, Spintronics VII, 91671B (28 August 2014); doi: 10.1117/12.2063079
Show Author Affiliations
T. Min, IMEC (Belgium)
G. S. Kar, IMEC (Belgium)
J. Swerts, IMEC (Belgium)
S. Mertens, IMEC (Belgium)
S. Coseman, IMEC (Belgium)
J. Bekaert, IMEC (Belgium)
K. Xu, IMEC (Belgium)
L. Souriau, IMEC (Belgium)
D. Radisic, IMEC (Belgium)
H. Okuyama, Canon ANELVA Corp. (Japan)
K. Nishimura, Canon ANELVA Corp. (Japan)
T. Seino, Canon ANELVA Corp. (Japan)
K. Tsunekawa, Canon ANELVA Corp. (Japan)


Published in SPIE Proceedings Vol. 9167:
Spintronics VII
Henri-Jean Drouhin; Jean-Eric Wegrowe; Manijeh Razeghi, Editor(s)

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