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Proceedings Paper

Hardware architecture for rapid generation of electro-holographic fringe patterns
Author(s): John A. Watlington; Mark E. Lucente; Carlton J. Sparrell; V. Michael Bove; Ichiro Tamitani
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Paper Abstract

This report describe the hardware architecture and software implementation of a hologram computing system developed at the MIT Media Laboratory. The hologram computing employs specialized stream-processing hardware embedded in the Cheops Image Processing system--a compact, block data-flow parallel processor. A superposition stream processor performs weighted summations of arbitrary 1D basis functions. A two-step holographic computation method--called Hogel-Vector encoding--utilizes the stream processor's computational power. An array of encoded hogel vectors, generated from a 3D scene description, is rapidly decoded using the processor. The resulting 36-megabyte holographic pattern is transferred to frame- buffers and then fed to a real-time electro-holographic display, producing 3D holographic images. System performance is sufficient to generate an image volume approximately 100 mm per side in 3 seconds. The architecture is scalable over a limited range in both display size and computational power. The limitations on system scalability will be identified and solutions proposed.

Paper Details

Date Published: 12 April 1995
PDF: 12 pages
Proc. SPIE 2406, Practical Holography IX, (12 April 1995); doi: 10.1117/12.206216
Show Author Affiliations
John A. Watlington, MIT Media Lab. (United States)
Mark E. Lucente, MIT Media Lab. (United States)
Carlton J. Sparrell, MIT Media Lab. (United States)
V. Michael Bove, MIT Media Lab. (United States)
Ichiro Tamitani, NEC Corp. (Japan)


Published in SPIE Proceedings Vol. 2406:
Practical Holography IX
Stephen A. Benton, Editor(s)

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