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Proceedings Paper

Hierarchical multiprocessor-based image-analysis system
Author(s): M. V. Raghunadh; M. V.G.V. Prasad Babu; J. P. Raina
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Paper Abstract

Hierarchial structures permit distributed computing and multitasking for processing the partitionable image data. A two level hierarchial multiprocessor employing the 68000 master processor, three 8085 slave processors, shared memory mapping, VME backplane bus and dedicated operating system is presented in this paper. The task generation, scheduling and interprocessor communication is under OS control. Image processing algorithms like edge detection, segmentation, smoothing and compression were performed by the master and slaves simultaneously.

Paper Details

Date Published: 23 March 1995
PDF: 7 pages
Proc. SPIE 2421, Image and Video Processing III, (23 March 1995); doi: 10.1117/12.205489
Show Author Affiliations
M. V. Raghunadh, Indian Institute of Technology Madras (India)
M. V.G.V. Prasad Babu, Indian Institute of Technology Madras (India)
J. P. Raina, Indian Institute of Technology Madras (India)

Published in SPIE Proceedings Vol. 2421:
Image and Video Processing III
Robert L. Stevenson; Sarah A. Rajala, Editor(s)

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