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Proceedings Paper

Wideband aperture array using RF channelizers and massively parallel digital 2D IIR filterbank
Author(s): Arindam Sengupta; Arjuna Madanayake; Roberto Gómez-García; Erik D. Engeberg
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Paper Abstract

Wideband receive-mode beamforming applications in wireless location, electronically-scanned antennas for radar, RF sensing, microwave imaging and wireless communications require digital aperture arrays that offer a relatively constant far-field beam over several octaves of bandwidth. Several beamforming schemes including the well-known true time-delay and the phased array beamformers have been realized using either finite impulse response (FIR) or fast Fourier transform (FFT) digital filter-sum based techniques. These beamforming algorithms offer the desired selectivity at the cost of a high computational complexity and frequency-dependant far-field array patterns. A novel approach to receiver beamforming is the use of massively parallel 2-D infinite impulse response (IIR) fan filterbanks for the synthesis of relatively frequency independent RF beams at an order of magnitude lower multiplier complexity compared to FFT or FIR filter based conventional algorithms. The 2-D IIR filterbanks demand fast digital processing that can support several octaves of RF bandwidth, fast analog-to-digital converters (ADCs) for RF-to-bits type direct conversion of wideband antenna element signals. Fast digital implementation platforms that can realize high-precision recursive filter structures necessary for real-time beamforming, at RF radio bandwidths, are also desired. We propose a novel technique that combines a passive RF channelizer, multichannel ADC technology, and single-phase massively parallel 2-D IIR digital fan filterbanks, realized at low complexity using FPGA and/or ASIC technology. There exists native support for a larger bandwidth than the maximum clock frequency of the digital implementation technology. We also strive to achieve More-than-Moore throughput by processing a wideband RF signal having content with N-fold (B = N Fclk/2) bandwidth compared to the maximum clock frequency Fclk Hz of the digital VLSI platform under consideration. Such increase in bandwidth is achieved without use of polyphase signal processing or time-interleaved ADC methods. That is, all digital processors operate at the same Fclk clock frequency without phasing, while wideband operation is achieved by sub-sampling of narrower sub-bands at the the RF channelizer outputs.

Paper Details

Date Published: 29 May 2014
PDF: 8 pages
Proc. SPIE 9077, Radar Sensor Technology XVIII, 90771G (29 May 2014); doi: 10.1117/12.2053050
Show Author Affiliations
Arindam Sengupta, The Univ. of Akron (United States)
Arjuna Madanayake, The Univ. of Akron (United States)
Roberto Gómez-García, Univ. de Alcalá (Spain)
Erik D. Engeberg, The Univ. of Akron (United States)

Published in SPIE Proceedings Vol. 9077:
Radar Sensor Technology XVIII
Kenneth I. Ranney; Armin Doerry, Editor(s)

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