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Proceedings Paper

Design and characterization of a readout circuit for FET-based THz imaging
Author(s): Suzana Domingues; Daniele Perenzoni; Matteo Perenzoni; David Stoppa
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Paper Abstract

A switched-capacitor integrator readout circuit for FET-based terahertz (THz) detectors was fabricated in a 0.13 μm standard CMOS technology. The designed readout circuit is suitable for implementation in pixel arrays due to its compact size and power consumption. In order to find the optimum bias point of the FET detector, responsivity, noise equivalent power (NEP) and signal-to-noise ratio (SNR) curves in function of the FET gate voltage (VG) have been measured for an arbitrary number of 10 accumulation cycles and two different operating clock frequencies. A responsivity peak of 1.8 kV/W was obtained with a clock frequency of 200 kHz, and of 1.3 kV/W at 400 kHz. A minimum NEP of 7.3 nW/√Hz was obtained with a 400 kHz clock frequency, while at 200 kHz the NEP is 8.5 nW/√Hz. The presented THz measurements with 100 accumulation cycles at 200 kHz and 400 kHz clock frequencies show a SNR improvement after each operation cycle, which means 500 and 1000 measurements per second with on-off modulation of the source, respectively. A test structure containing only a FET detector and a bowtie THz antenna was used to evaluate the impact of the readout circuit in the FET THz detection.

Paper Details

Date Published: 15 May 2014
PDF: 8 pages
Proc. SPIE 9141, Optical Sensing and Detection III, 914105 (15 May 2014); doi: 10.1117/12.2052181
Show Author Affiliations
Suzana Domingues, Fondazione Bruno Kessler (Italy)
Daniele Perenzoni, Fondazione Bruno Kessler (Italy)
Matteo Perenzoni, Fondazione Bruno Kessler (Italy)
David Stoppa, Fondazione Bruno Kessler (Italy)


Published in SPIE Proceedings Vol. 9141:
Optical Sensing and Detection III
Francis Berghmans; Anna G. Mignani; Piet De Moor, Editor(s)

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