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Proceedings Paper

Realization of a neuronal hardware with digital signal processor and programmable gate arrays
Author(s): Anke Meyer-Baese; Uwe Meyer-Baese; Henning Scheich
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Paper Abstract

In this paper we describe how the processing speed of a radial basis neural network can be performed by the use of field programmable gate arrays (FPGA). The calculation of the very time-consuming exponential function is taken by an optimized CORDIC-processor. We determine the number of the necessary FPGAs and do a processing speed comparison between FPGA and DSP referring to an application in speech recognition.

Paper Details

Date Published: 6 April 1995
PDF: 8 pages
Proc. SPIE 2492, Applications and Science of Artificial Neural Networks, (6 April 1995); doi: 10.1117/12.205092
Show Author Affiliations
Anke Meyer-Baese, Technische Hochschule Darmstadt (Germany)
Uwe Meyer-Baese, Technische Hochschule Darmstadt (Germany)
Henning Scheich, Institut fuer Neurobiologie (Germany)

Published in SPIE Proceedings Vol. 2492:
Applications and Science of Artificial Neural Networks
Steven K. Rogers; Dennis W. Ruck, Editor(s)

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