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Proceedings Paper

Patterning challenges in the fabrication of 12 nm half-pitch dual damascene copper ultra low-k interconnects
Author(s): J. S. Chawla; K. J. Singh; A. Myers; D. J. Michalak; R. Schenker; C. Jezewski; B. Krist; F. Gstrein; T. K. Indukuri; H. J. Yoo
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Paper Abstract

Earlier [1, 2] work highlighted an integrated process for electrically functional 12 nm half-pitch copper interconnects in an ultralow-k interlayer dielectric (ILD). In this paper, we focus on understanding and reducing undesired effects such as pattern asymmetry/distortion, and line undulation/ collapse. Key defect modes and possible solution paths are discussed. Line undulation can occur when the ILD feature changes shape under the stress of the sacrificial hard mask(s) (HM) during patterning, resulting in “wavy” instead of straight features. The amount of undulation is directly related to mechanical properties such as elastic modulus, residual stresses of patterned HMs and the ILD, as well as the dimensions and aspect ratio of the features. Line collapse is observed post wet-clean processing when one or more of the following is true - Insufficient ILD mechanical strength, excessive pattern aspect ratio, or non-uniform drying. Pattern asymmetry, or unequal critical dimensions (CD) of trenches defined by the same backbone, is a typical problem encountered during spacer-based pitch division. In pitch quartering (P/4), three different trench widths result from small variations in backbone lithography, spacer CD and etch bias. Symmetric patterning can be achieved through rigorous control of patterning processes like backbone definition, spacer deposition and downstream etches. Plasma-based ash and energetic metal deposition were also observed to degrade patterning fidelity of ultra low-k film, and also need to be closely managed.

Paper Details

Date Published: 28 March 2014
PDF: 8 pages
Proc. SPIE 9054, Advanced Etch Technology for Nanopatterning III, 905404 (28 March 2014); doi: 10.1117/12.2048599
Show Author Affiliations
J. S. Chawla, Intel Corp. (United States)
K. J. Singh, Intel Corp. (United States)
A. Myers, Intel Corp. (United States)
D. J. Michalak, Intel Corp. (United States)
R. Schenker, Intel Corp. (United States)
C. Jezewski, Intel Corp. (United States)
B. Krist, Intel Corp. (United States)
F. Gstrein, Intel Corp. (United States)
T. K. Indukuri, Intel Corp. (United States)
H. J. Yoo, Intel Corp. (United States)

Published in SPIE Proceedings Vol. 9054:
Advanced Etch Technology for Nanopatterning III
Gottlieb S. Oehrlein; Qinghuang Lin; Ying Zhang, Editor(s)

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