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Proceedings Paper

Topographic and other effects on EUV pattern fidelity
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Paper Abstract

The ability to incorporate topographic and other effects of previously patterned layers in ground rule formulation could potentially lead to significant cost savings and shortened time needed for technology ramp-up. The effect of topgraphy coupled with the diminishing depth of focus (DOF) associated with design node shrinks could become a significant yield detractor. With migration of transistor architecture from planer CMOS to 3-D FINFETs, such topographic effect could potentially pose a major challenge for future EUV processes even with significantly lower NA (Numerical Aperture) compared to current immersion DUV processes. We review how resist parameters for a given layer can be optimized to minimize imaging artifacts caused by underlying topography of previous layers. We also demonstrate how residual effects after resist parameter optimization could be handled by a sets of interlayer groundrules or novel OPC methods. Initially we study standard immersion ArF processing, then we extend the methodology to evaluate the potential issues with EUV lithography in the presence of topography. We compare the the nature and magnitude of the topography effects of such results with DUV imaging and show how we can design a new resist system to minimize such effects. We also show how future ground rule development might need to incorporate the layout information of the previously patterned layers.

Paper Details

Date Published: 31 March 2014
PDF: 9 pages
Proc. SPIE 9052, Optical Microlithography XXVII, 905206 (31 March 2014); doi: 10.1117/12.2047920
Show Author Affiliations
Chandra Sarma, SEMATECH Inc. (United States)
Trey Graves, KLA-Tencor Texas (United States)
Mark Neisser, SEMATECH Inc. (United States)
Stewart Robertson, KLA-Tencor Texas (United States)

Published in SPIE Proceedings Vol. 9052:
Optical Microlithography XXVII
Kafai Lai; Andreas Erdmann, Editor(s)

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