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Proceedings Paper

Metrology of white light interferometer for TSV processing
Author(s): Padraig Timoney; Yeong-Uk Ko; Daniel Fisher; Cheng Kuan Lu; Yudesh Ramnath; Alok Vaid; Sarasvathi Thangaraju; Daniel Smith; Himani Kamineni; Dingyou Zhang; Wonwoo Kim; Ramakanth Alapati; Jonathan Peak; Hemant Amin; Holly Edmunson; Joe Race; Brennan Peterson; Tim Johnson
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Paper Abstract

3D integration technology offers an alternative to traditional packaging designs. In traditional Moore’s law scaling, features are added to the die, with graphics, memory control and logic coprocessors all integrated onto the silicon chip. TSV (through silicon via) processing utilizes vertical electrical interconnects that provide the shortest possible path to establish an electrical connection from the device side to the backside of a die. This indirectly allows continues “Moore”- like scaling while only affecting the device packaging. White light interferometry (WLI) has been used for the measurement of topography, step height and via depth using its short coherence length. The nanometer level resolution of this technique is ideal for TSV measurements in the high aspect ratio vias. In this work, six white light interferometer measurements for TSV processing are discussed along with the importance of these measurements to TSV processing, namely: 1. Post-TSV etch: depth, top CD (TCD) and bottom CD (BCD) 2. Post-TSV liner BCD 3. Post-TSV barrier seed BCD 4. TSV electro-chemically plated (ECP) copper bump step height 5. Post-annealing bump step height 6. TSV CMP dishing These measurement steps have been implemented in-line for advanced technology node TSV process flows at GLOBALFOUNDRIES. The measurements demonstrate 90% correlation to reference metrology and <0.5% repeatability. Cross section SEM was used as a reference for TSV profile and Cu bump measurements while AFM was used as a reference for dishing measurements.

Paper Details

Date Published: 2 April 2014
PDF: 8 pages
Proc. SPIE 9050, Metrology, Inspection, and Process Control for Microlithography XXVIII, 90500F (2 April 2014); doi: 10.1117/12.2047383
Show Author Affiliations
Padraig Timoney, GLOBALFOUNDRIES Inc. (United States)
Yeong-Uk Ko, GLOBALFOUNDRIES Inc. (United States)
Daniel Fisher, GLOBALFOUNDRIES Inc. (United States)
Cheng Kuan Lu, GLOBALFOUNDRIES Inc. (United States)
Yudesh Ramnath, GLOBALFOUNDRIES Inc. (United States)
Alok Vaid, GLOBALFOUNDRIES Inc. (United States)
Sarasvathi Thangaraju, GLOBALFOUNDRIES Inc. (United States)
Daniel Smith, GLOBALFOUNDRIES Inc. (United States)
Himani Kamineni, GLOBALFOUNDRIES Inc. (United States)
Dingyou Zhang, GLOBALFOUNDRIES Inc. (United States)
Wonwoo Kim, GLOBALFOUNDRIES Inc. (United States)
Ramakanth Alapati, GLOBALFOUNDRIES Inc. (United States)
Jonathan Peak, Nanometrics Inc. (United States)
Hemant Amin, Nanometrics Inc. (United States)
Holly Edmunson, Nanometrics Inc. (United States)
Joe Race, Nanometrics Inc. (United States)
Brennan Peterson, Nanometrics Inc. (United States)
Tim Johnson, Nanometrics Inc. (United States)

Published in SPIE Proceedings Vol. 9050:
Metrology, Inspection, and Process Control for Microlithography XXVIII
Jason P. Cain; Martha I. Sanchez, Editor(s)

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