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Proceedings Paper

Directed self-assembly process integration: Fin patterning approaches and challenges
Author(s): Safak Sayan; B. T. Chan; Roel Gronheid; Frieda Van Roey; Min-Soo Kim; Lance Williamson; Paul Nealey
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Paper Abstract

Resolution requirements for photolithography have reached beyond the wavelength of light. Consequently, it is becoming increasingly complicated and expensive to further minimize feature dimensions as required to push the limits of Moore’s law. EUV lithography has been the much anticipated solution; however, its insertion timing for High Volume Manufacturing is still an uncertainty due to source power and EUV mask infrastructure limitations. Extending the limits of 193nm immersion lithography requires pitch division using either Double Patterning Pitch Division (DPPD), and/or Spacer Based Pitch Division (SBPD) schemes (e.g. Hard mask image transfer methods (Double, Triple, Quadruple)). While these approaches reduce pitch, there is an associated risk/compromise of process complexity, and overlay accuracy budget issues. Directed Self Assembly (DSA) processes offer the promise of providing alternative ways to extend optical lithography cost-effectively for sub-10nm nodes and present itself as an alternative pitch division approach. As a result, DSA has gained increased momentum in recent years, as a means for extending optical lithography past its current limits. The availability of a DSA processing line can enable to further push the limits of 193nm immersion lithography and overcome some of the critical concerns for EUV lithography. Robust etch transfer of DSA patterns into commonly used device integration materials such as silicon, silicon nitride, and silicon dioxide had been previously demonstrated [1,2]. However DSA integration to CMOS process flows, including cut/keep structures to form fin arrays, is yet to be demonstrated on relevant film stacks (front-end-of-line device integration such as hard mask stacks, and STI stacks). Such a demonstration will confirm and reinforce its viability as a candidate for sub-10nm technology nodes.

Paper Details

Date Published: 27 March 2014
PDF: 9 pages
Proc. SPIE 9051, Advances in Patterning Materials and Processes XXXI, 90510M (27 March 2014); doi: 10.1117/12.2047268
Show Author Affiliations
Safak Sayan, Intel Corp. (United States)
IMEC (Belgium)
B. T. Chan, IMEC (Belgium)
Roel Gronheid, IMEC (Belgium)
Frieda Van Roey, IMEC (Belgium)
Min-Soo Kim, IMEC (Belgium)
Lance Williamson, IMEC (Belgium)
The Univ. of Chicago (United States)
Paul Nealey, The Univ. of Chicago (United States)


Published in SPIE Proceedings Vol. 9051:
Advances in Patterning Materials and Processes XXXI
Thomas I. Wallow; Christoph K. Hohle, Editor(s)

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