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Proceedings Paper

Full-chip model-based OPC verification by using rigorous resist 3D model
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Paper Abstract

As design rule of devices are getting smaller, it is hard to obtain enough process window like DOF, EL. In aspect of device integration, lithography processes which are included in etching process became more and more important. It has been claimed that photo resist profile is closely related with etch bias and vertical profile. Resist top-loss and bottom slope seriously affect after-etching profile. In order to address these problems, new model based verification method is necessary for preventing hot spots. In this paper, we propose more practical method of model based verification using rigorous simulation and wafer verification results. Highly accurate model is obtained by physical model fitting with minimal experimental data set. After that, virtual data are extracted from rigorous simulation model for applying full chip model based verification modeling. Basically, 2 data sets will be needed for verification of 2-level model, for detecting resist top-loss and bottom-slope. Finally this article shows comparison results of model based verification and real wafer inspection. And also, we try to prove that the newly proposed method is another good candidate to address existing problems such as pinching and bridging after post etching and CMP process.

Paper Details

Date Published: 31 March 2014
PDF: 8 pages
Proc. SPIE 9052, Optical Microlithography XXVII, 905220 (31 March 2014); doi: 10.1117/12.2046577
Show Author Affiliations
Dongho Kong, SK Hynix, Inc. (Korea, Republic of)
Taejun You, SK Hynix, Inc. (Korea, Republic of)
Cheolkyun Kim, SK Hynix, Inc. (Korea, Republic of)
Hyunjo Yang, SK Hynix, Inc. (Korea, Republic of)
Donggyu Yim, SK Hynix, Inc. (Korea, Republic of)


Published in SPIE Proceedings Vol. 9052:
Optical Microlithography XXVII
Kafai Lai; Andreas Erdmann, Editor(s)

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