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Proceedings Paper

Layout induced variability and manufacturability checks in FinFETs process
Author(s): Yongchan Ban; Jason Sweis; Philippe Hurat; Ya-Chieh Lai; Yongseok Kang; Woo Hyun Paik; Wei Xu; Huiyuan Song
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Paper Abstract

With increasing chip sizes and shrinking device dimensions, on-chip semiconductor process variation can no longer be ignored in the design and signoff static timing analysis of integrated circuits. An important parameter affecting CMOS technologies is the gate length (Lgate) of a transistor. In modern technologies significant spatial intra-chip variability of transistor gate lengths which are systematic, as opposed to random, can lead to relatively large variations in circuit path delays. Spatial variations in Lgate affect circuit timing properties, which can lead to timing errors and performance loss. To maximize performance and process utilization in microprocessor designs, we have developed and validated a timing analysis methodology based on accurate silicon contour prediction from drawn layout and contour-based extraction of our designs. This allows for signoff timing without unnecessarily large margins, thereby reducing chip area and maximizing performance while ensuring chip functionality, improved process utilization and yield. In this paper we describe such a chip timing methodology, its validation and implementation in microprocessor design. We also report results of layout optimization based on new pattern matching technology.

Paper Details

Date Published: 28 March 2014
PDF: 7 pages
Proc. SPIE 9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 90530I (28 March 2014); doi: 10.1117/12.2046284
Show Author Affiliations
Yongchan Ban, LG Electronics Inc. (Korea, Republic of)
Jason Sweis, Cadence Design Systems, Inc. (United States)
Philippe Hurat, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)
Yongseok Kang, LG Electronics Inc. (Korea, Republic of)
Woo Hyun Paik, LG Electronics Inc. (Korea, Republic of)
Wei Xu, Cadence Design Systems, Inc. (United States)
Huiyuan Song, Cadence Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 9053:
Design-Process-Technology Co-optimization for Manufacturability VIII
John L. Sturtevant; Luigi Capodieci, Editor(s)

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