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Proceedings Paper

Model-based pattern dummy generation for logic devices
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Paper Abstract

The insertion of SRAF(Sub-Resolution Assist Feature) is one of the most frequently used method to enlarge the process window area. In most cases, the size of SRAF is proportional to the focus margin of drawn patterns. However, there is a trade-off between the SRAF size and SRAF printing, because SRAF is not supposed to be patterned on a wafer. For this reason, a lot of OPC engineers have been tried to put bigger and more SRAFs within the limits of the possible. The fact that many papers about predicting SRAF printability have been published recent years reflects this circumstance. Pattern dummy is inserted to enhance the lithographic process margin and CD uniformity unlike CMP dummy for uniform metal line height. It is ordinary to put pattern dummy at the designated location under consideration of the pitch of real patterns at design step. However, it is not always desirable to generate pattern dummies based on rules at the lithographic point of view. In this paper, we introduce the model based pattern dummy insertion method, which is putting pattern dummies at the location that model based SRAF is located. We applied the model based pattern dummy to the layers in logic devices, and studied which layer is more efficient for the insertion of dummies.

Paper Details

Date Published: 31 March 2014
PDF: 7 pages
Proc. SPIE 9052, Optical Microlithography XXVII, 90521W (31 March 2014); doi: 10.1117/12.2046198
Show Author Affiliations
Jongwon Jang, SK Hynix, Inc. (Korea, Republic of)
Cheolkyun Kim, SK Hynix, Inc. (Korea, Republic of)
Sungwoo Ko, SK Hynix, Inc. (Korea, Republic of)
Seokyoung Byun, SK Hynix, Inc. (Korea, Republic of)
Hyunjo Yang, SK Hynix, Inc. (Korea, Republic of)
Donggyu Yim, SK Hynix, Inc. (Korea, Republic of)

Published in SPIE Proceedings Vol. 9052:
Optical Microlithography XXVII
Kafai Lai; Andreas Erdmann, Editor(s)

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