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Proceedings Paper

Synthesis of lithography test patterns through topology-oriented pattern extraction and classification
Author(s): Seongbo Shim; Woohyun Chung; Youngsoo Shin
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Paper Abstract

Comprehensive and compact test patterns are crucial to the development of new semiconductor technology. In particular, the random nature of routing layers tends to create many hotspots, corresponding to patterns which are difficult to predict. Conventional group of test patterns consists of parametric typical patterns and real layout clips, which contain a lot of redundancy. The paper addresses a problem of generating comprehensive yet compact group of test patterns for random routing layers. A new method of pattern extraction and classification is proposed to solve the problem.

Paper Details

Date Published: 28 March 2014
PDF: 10 pages
Proc. SPIE 9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 905305 (28 March 2014); doi: 10.1117/12.2046142
Show Author Affiliations
Seongbo Shim, KAIST (Korea, Republic of)
Woohyun Chung, KAIST (Korea, Republic of)
Youngsoo Shin, KAIST (Korea, Republic of)


Published in SPIE Proceedings Vol. 9053:
Design-Process-Technology Co-optimization for Manufacturability VIII
John L. Sturtevant; Luigi Capodieci, Editor(s)

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