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Proceedings Paper

Layout pattern-driven design rule evaluation
Author(s): Yasmine Badr; Ko-wei Ma; Puneet Gupta
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Paper Abstract

With the use of sub-wavelength photolithography, some layouts can have low printability and, accordingly, low yield due to the existence of bad patterns, even though they pass design rule checks. A reasonable approach is to select some of the candidate bad patterns as “forbidden”. With the use of sub-wavelength photolithography, some layouts can have low printability and, accordingly, low yield due to the existence of bad patterns, even though they pass design rule checks. A reasonable approach is to select some of the candidate bad patterns as forbidden". These are the ones with high yield-impact or low routability-impact, and these are to be prohibited in the design phase. The rest of the candidate bad patterns may be fixed in the post-route stage, in a best-effort manner. The process developers need to optimize the process to be friendly to the patterns of high routability-impact. Hence, an evaluation method is required early in the process, to assess the impact of forbidding layout patterns on routability. In this work, we propose Pattern-driven Design Rule Evaluation (Pattern-DRE), which can be used to evaluate the importance of patterns for the routability of the standard cells and, accordingly, select the set of bad patterns to forbid in the design. The framework can also be used to compare restrictive patterning technologies (e.g. LELE, SADP, SAQP, SAOP). Given a set of design rules and a set of forbidden patterns, Pattern-DRE generates a set of virtual standard cells, then it finds the possible routing options for each cell, without using any of the forbidden patterns. Finally, it reports the routability metrics. We present few studies that illustrate the use cases of the framework. The first study compares LELE to SADP, by using a set of forbidden patterns that are allowed by LELE but not by SADP. The second study investigates the area penalty as well as the SADP-compliance that we obtain if we increase the minimum gate-to-Local-Interconnect spacing design rule.

Paper Details

Date Published: 28 March 2014
PDF: 10 pages
Proc. SPIE 9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 905307 (28 March 2014); doi: 10.1117/12.2046140
Show Author Affiliations
Yasmine Badr, Univ. of California, Los Angeles (United States)
Ko-wei Ma, NVIDIA Inc. (United States)
Puneet Gupta, Univ. of California, Los Angeles (United States)


Published in SPIE Proceedings Vol. 9053:
Design-Process-Technology Co-optimization for Manufacturability VIII
John L. Sturtevant; Luigi Capodieci, Editor(s)

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