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Proceedings Paper

Study of the pattern aware OPC
Author(s): Shin-Shing Yeh; Alan Zhu; James Chen; Bayram Yenikaya; Yi-Shiang Chang; Chia-Chi Lin
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Paper Abstract

It’s critical to address the yield issues caused by process specific layout patterns with limited process window. RETs such as PWOPC are introduced to guarantee high lithographic margin, but these techniques cost high run-time when applied to full-chips. There’s also lack of integrated solution to easily identify, define comprehensive patterns and apply different controls and/or constraints over these patterns through different stages of OPC/RET process. In this paper, we study a pattern aware OPC flow that applies PWOPC or specific corrections locally to layouts with critical and yield limiting patterns. Although the full chip PWOPC provides an effective way, it causes great amount of run time penalty and does not achieve optimal process window. Overall, PAOPC achieves the better margins over the hotspots, without sacrificing turnaround time. The study demonstrates the benefit of the new flow with fine grained process window controls over different patterns. This flow get good improvement on defect counts when evaluated on 50 nm node logic devices.

Paper Details

Date Published: 31 March 2014
PDF: 9 pages
Proc. SPIE 9052, Optical Microlithography XXVII, 90521Y (31 March 2014); doi: 10.1117/12.2046059
Show Author Affiliations
Shin-Shing Yeh, Powerchip Semiconductor Corp. (Taiwan)
Alan Zhu, Cadence Design Systems, Inc. (United States)
James Chen, Cadence Design Systems, Inc. (United States)
Bayram Yenikaya, Cadence Design Systems, Inc. (United States)
Yi-Shiang Chang, Powerchip Semiconductor Corp. (Taiwan)
Chia-Chi Lin, Powerchip Semiconductor Corp. (Taiwan)

Published in SPIE Proceedings Vol. 9052:
Optical Microlithography XXVII
Kafai Lai; Andreas Erdmann, Editor(s)

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