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Proceedings Paper

Pattern-based full-chip process verification
Author(s): Changsheng Ying; Yongjun Kwon; Paul Fornari; Gökhan Perçin; Anwei Liu
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Paper Abstract

This paper discusses a novel pattern based standalone process verification technique that meets with current and future needs for semiconductor manufacturing of memory and logic devices. The choosing the right process verification technique is essential to bridge the discrepancy between the intended and the printed pattern. As the industry moving to very low k1 patterning solutions at each technology node, the challenges for process verification are becoming nightmare for lithography engineers, such as large number of possible verification defects and defect disposition. In low k1 lithography, demand for full-chip process verification is increasing. Full-chip process verification is applied post to process and optical proximity correction (OPC) step. The current challenges in process verification are large number of defects reported, disposition difficulties, long defect review times, and no feedback provided to OPC. The technique presented here is based on pattern based verification where each reported defects are classified in terms of patterns and these patterns are saved to a database. Later this database is used for screening incoming new design prior to OPC step.

Paper Details

Date Published: 31 March 2014
PDF: 6 pages
Proc. SPIE 9052, Optical Microlithography XXVII, 905212 (31 March 2014); doi: 10.1117/12.2046045
Show Author Affiliations
Changsheng Ying, Cadence Design Systems, Inc. (United States)
Yongjun Kwon, Cadence Design Systems, Inc. (United States)
Paul Fornari, Cadence Design Systems, Inc. (United States)
Gökhan Perçin, Cadence Design Systems, Inc. (United States)
Anwei Liu, Cadence Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 9052:
Optical Microlithography XXVII
Kafai Lai; Andreas Erdmann, Editor(s)

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