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Proceedings Paper

Demonstrating production quality multiple exposure patterning aware routing for the 10NM node
Author(s): Lars Liebmann; Vassilios Gerousis; Paul Gutwin; Mike Zhang; Geng Han; Brian Cline
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Paper Abstract

This paper reviews the escalation in design constraints imposed on 2nd level wiring by multiple patterning exposure techniques in the 10NM technology node (i.e. ~45nm wiring pitch) relative to the 14NM technology node (i.e. 64nm wiring pitch). Specifically, new challenges facing place-and-route tooling are outlined, solutions to overcome these challenges are reviewed, and a manufacturing ready implementation is demonstrated.

Paper Details

Date Published: 28 March 2014
PDF: 10 pages
Proc. SPIE 9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 905309 (28 March 2014); doi: 10.1117/12.2045958
Show Author Affiliations
Lars Liebmann, IBM Corp. (United States)
Vassilios Gerousis, Cadence Design Systems, Inc. (United States)
Paul Gutwin, Cadence Design Systems, Inc. (United States)
Mike Zhang, Cadence Design Systems, Inc. (United States)
Geng Han, IBM Corp. (United States)
Brian Cline, ARM Inc. (United States)

Published in SPIE Proceedings Vol. 9053:
Design-Process-Technology Co-optimization for Manufacturability VIII
John L. Sturtevant; Luigi Capodieci, Editor(s)

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