Share Email Print
cover

Proceedings Paper

28nm FDSOI high-K metal gate CD variability investigation
Author(s): L. Desvoivres; P. Gouraud; B. Le Gratiet; R. Bouyssou; R. Ranica; C. Gallon; I. Thomas
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Planar Fully-Depleted (FD) Silicon On Insulator (SOI) MOSFET technology has already demonstrated large performance boost vs bulk at 28nm node (>30%) and is very competitive for incoming mobile & multimedia products thanks to design porting from bulk. Indeed, FDSOI is very attractive for low power applications due to its low sub threshold slope (~60mV/dec), better short channel effect (SCE) control and reduced junction capacitance. 28nm FDSOI devices highly depend on gate CD morphology because electrical effective gate length is driven by metal gate CD. High-k metal gate etching is therefore a key point to achieve these requirements. Gate profiles and metal gate CD control are mandatory and variability has to be minimized across the wafer (WiW), wafer to wafer and lot to lot. In this paper, we will focus on metal gate CD variability investigation. Once polysilicon gate profiles are frozen, metal gate profiles adjustment is achieved, based on scatterometry metal gate profiles measurements, TEM analysis and electrical results. Thanks to this methodology, a metal gate etching process has been tuned on 300mm industrial platform etcher. This work was performed at ST Crolles 300 facility in collaboration between STMicroelectronics & CEA/LETI.

Paper Details

Date Published: 28 March 2014
PDF: 7 pages
Proc. SPIE 9054, Advanced Etch Technology for Nanopatterning III, 905408 (28 March 2014); doi: 10.1117/12.2045904
Show Author Affiliations
L. Desvoivres, CEA-LETI (France)
P. Gouraud, STMicroelectronics (France)
B. Le Gratiet, STMicroelectronics (France)
R. Bouyssou, STMicroelectronics (France)
R. Ranica, STMicroelectronics (France)
C. Gallon, STMicroelectronics (France)
I. Thomas, STMicroelectronics (France)


Published in SPIE Proceedings Vol. 9054:
Advanced Etch Technology for Nanopatterning III
Gottlieb S. Oehrlein; Qinghuang Lin; Ying Zhang, Editor(s)

© SPIE. Terms of Use
Back to Top