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Proceedings Paper

Across wafer CD uniformity optimization by wafer film scheme at double patterning lithography process
Author(s): Hsiao-Chiang Lin; Yang-Liang Li; Shiuan-Chuan Wang; Chien-Hung Liu; Zih-Song Wang; Jhung-Yuin Hsuh
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Paper Abstract

The Double Patterning lithography (DPL) process is a well known method to overcome the k1 limit below 0.25, but the pattern final performance (OVL/CD) get more sensitive with the initial core CD uniformity, one of the main factors is across wafer CD uniformity control. Previous improvements applying scanner dose or PEB temperature multi-zone control, the others use the vacuum PEB plate design. In this study, we adopt various DPL sacrificial layers to modify wafer warpage level, it can adjust a suitable wafer warpage profile. By this method, we can achieve 30% CD uniformity improvement without the scanner dose/ PEB multi-zone heating compensation,

Paper Details

Date Published: 2 April 2014
PDF: 6 pages
Proc. SPIE 9050, Metrology, Inspection, and Process Control for Microlithography XXVIII, 905026 (2 April 2014); doi: 10.1117/12.2045875
Show Author Affiliations
Hsiao-Chiang Lin, Powerchip Technology Corp. (Taiwan)
Yang-Liang Li, Powerchip Technology Corp. (Taiwan)
Shiuan-Chuan Wang, Powerchip Technology Corp. (Taiwan)
Chien-Hung Liu, Powerchip Technology Corp. (Taiwan)
Zih-Song Wang, Powerchip Technology Corp. (Taiwan)
Jhung-Yuin Hsuh, Powerchip Technology Corp. (Taiwan)


Published in SPIE Proceedings Vol. 9050:
Metrology, Inspection, and Process Control for Microlithography XXVIII
Jason P. Cain; Martha I. Sanchez, Editor(s)

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