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Proceedings Paper

DSA-aware detailed routing for via layer optimization
Author(s): Yuelin Du; Zigang Xiao; Martin D. F. Wong; He Yi; H.-S. Philip Wong
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Paper Abstract

In detailed routing for integrated circuit (IC) designs, vias are usually randomly inserted in order to connect between di erent routing layers. In the 7 nm technology node and beyond, the wire pitch is below 40 nm, and consequently, the vias become very dense, making via layer printing a challenging problem. Recently block copolymer directed self-assembly (DSA) technology has demonstrated great advantages for via layer patterning using guiding templates. To pattern vias with DSA process, guiding templates are usually printed rst with conventional lithography, e:g:, 193 nm immersion lithography (193i) that has a coarser pitch resolution. Then the guiding templates will guide the placement of the DSA patterns (e:g:, vias) inside, and these patterns have a ner resolution than the templates. Di erent template shapes have di erent control on the overlay accuracy of the inside vias. By performing DSA experiments, the guiding templates can be classi ed as feasible and infeasible templates according to the overlay requirement of the technology node. The templates that meet the overlay requirement are feasible templates, and other templates are infeasible. Without considering the DSA template constraints in detailed routing, randomly distributed vias may require infeasible templates to be patterned, which makes the via layers incompatible with the DSA process. In this paper, we propose a DSA-aware detail routing algorithm to optimize the via layers such that only feasible templates are needed for via layer patterning. In addition, among all the feasible templates, the one with better overlay accuracy has higher priority to be picked up by the router for via patterning, which further improves the yield. By enabling DSA process for via layer patterning in the 7 nm technology node, the proposed detailed routing strategy tremendously reduces the manufacturing cost and improves the throughput for IC fabrication.

Paper Details

Date Published: 28 March 2014
PDF: 8 pages
Proc. SPIE 9049, Alternative Lithographic Technologies VI, 90492J (28 March 2014); doi: 10.1117/12.2045756
Show Author Affiliations
Yuelin Du, Univ. of Illinois at Urbana-Champaign (United States)
Zigang Xiao, Univ. of Illinois at Urbana-Champaign (United States)
Martin D. F. Wong, Univ. of Illinois at Urbana-Champaign (United States)
He Yi, Stanford Univ. (United States)
H.-S. Philip Wong, Stanford Univ. (United States)

Published in SPIE Proceedings Vol. 9049:
Alternative Lithographic Technologies VI
Douglas J. Resnick; Christopher Bencher, Editor(s)

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