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Proceedings Paper

Optimizing standard cell design for quality
Author(s): Chimin Yuan; Dave Tipple; Jeff Warner
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Paper Abstract

To date, majority of the papers presented in the conference focused on how to print smaller transistors that run faster. In a different market such as safety-focused automotive market, “smaller and faster” are replaced by “tougher and living longer”. In such a market, a chip has to endure a wide range of operating temperature from -40C to 150C, and is required to have an extremely low field failure rate over 10+ years. There is a wide range of design techniques that can be deployed to improve the quality of a chip. In this paper, we present some of these design techniques that are related to the physical aspects of standard cells.

Paper Details

Date Published: 28 March 2014
PDF: 8 pages
Proc. SPIE 9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 90530O (28 March 2014); doi: 10.1117/12.2045660
Show Author Affiliations
Chimin Yuan, Freescale Semiconductor, Inc. (United States)
Dave Tipple, Freescale Semiconductor, Inc. (United States)
Jeff Warner, Freescale Semiconductor, Inc. (United States)

Published in SPIE Proceedings Vol. 9053:
Design-Process-Technology Co-optimization for Manufacturability VIII
John L. Sturtevant; Luigi Capodieci, Editor(s)

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