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Physical verification and manufacturing of contact/via layers using grapho-epitaxy DSA processes
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Paper Abstract

This paper extends the state of the art by describing the practical material’s challenges, as well as approaches to minimize their impact in the manufacture of contact/via layers using a grapho-epitaxy directed self assembly (DSA) process. Three full designs have been analyzed from the point of view of layout constructs. A construct is an atomic and repetitive section of the layout which can be analyzed in isolation. Results indicate that DSA’s main benefit is its ability to be resilient to the shape of the guiding pattern across process window. The results suggest that directed self assembly can still be guaranteed even with high distortion of the guiding patterns when the guiding patterns have been designed properly for the target process. Focusing on a 14nm process based on 193i lithography, we present evidence of the need of DSA compliance methods and mask synthesis tools which consider pattern dependencies of adjacent structures a few microns away. Finally, an outlook as to the guidelines and challenges to DSA copolymer mixtures and process are discussed highlighting the benefits of mixtures of homo polymer and diblock copolymer to reduce the number of defects of arbitrarily placed hole configurations.

Paper Details

Date Published: 28 March 2014
PDF: 8 pages
Proc. SPIE 9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 90530R (28 March 2014); doi: 10.1117/12.2045328
Show Author Affiliations
J. Andres Torres, Mentor Graphics Corp. (United States)
Kyohei Sakajiri, Mentor Graphics Corp. (United States)
David Fryer, Mentor Graphics Corp. (United States)
Yuri Granik, Mentor Graphics Corp. (United States)
Yuansheng Ma, Mentor Graphics Corp. (United States)
Polina Krasnova, Mentor Graphics Corp. (Russian Federation)
Germain Fenger, Mentor Graphics Corp. (Belgium)
Seiji Nagahara, Tokyo Electron Ltd. (Japan)
Shinichiro Kawakami, Tokyo Electron Kyushu Ltd. (Japan)
Benjamen Rathsack, Tokyo Electron America, Inc. (United States)
Gurdaman Khaira, Univ. of Chicago (United States)
Juan de Pablo, Univ. of Chicago (United States)
Julien Ryckaert, IMEC (Belgium)

Published in SPIE Proceedings Vol. 9053:
Design-Process-Technology Co-optimization for Manufacturability VIII
John L. Sturtevant; Luigi Capodieci, Editor(s)

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