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Proceedings Paper

Optical RAM-enabled cache memory and optical routing for chip multiprocessors: technologies and architectures
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Paper Abstract

The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.

Paper Details

Date Published: 8 March 2014
PDF: 8 pages
Proc. SPIE 8991, Optical Interconnects XIV, 89910Z (8 March 2014); doi: 10.1117/12.2042732
Show Author Affiliations
Nikos Pleros, Aristotle Univ. of Thessaloniki (Greece)
Ctr. for Research and Technology Hellas (Greece)
Pavlos Maniotis, Aristotle Univ. of Thessaloniki (Greece)
Ctr. for Research and Technology Hellas (Greece)
Theonitsa Alexoudi, Aristotle Univ. of Thessaloniki (Greece)
Ctr. for Research and Technology Hellas (Greece)
Dimitris Fitsios, Aristotle Univ. of Thessaloniki (Greece)
Ctr. for Research and Technology Hellas (Greece)
Christos Vagionas, Aristotle Univ. of Thessaloniki (Greece)
Ctr. for Research and Technology Hellas (Greece)
Sotiris Papaioannou, Aristotle Univ. of Thessaloniki (Greece)
Ctr. for Research and Technology Hellas (Greece)
K. Vyrsokinos, Ctr. for Research and Technology Hellas (Greece)
George T. Kanellos, Ctr. for Research and Technology Hellas (Greece)


Published in SPIE Proceedings Vol. 8991:
Optical Interconnects XIV
Henning Schröder; Ray T. Chen; Alexei L. Glebov, Editor(s)

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