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Proceedings Paper

A wide bandwidth analog front-end circuit for 60-GHz wireless communication receiver
Author(s): M. Furuta; H. Okuni; M. Hosoya; A. Sai; J. Matsuno; S. Saigusa; T. Itakura
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Paper Abstract

This paper presents an analog front-end circuit for a 60-GHz wireless communication receiver. The feature of the proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed. Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65nm CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224 mW Power consumption.

Paper Details

Date Published: 7 March 2014
PDF: 9 pages
Proc. SPIE 8985, Terahertz, RF, Millimeter, and Submillimeter-Wave Technology and Applications VII, 89851A (7 March 2014); doi: 10.1117/12.2039292
Show Author Affiliations
M. Furuta, Toshiba Corp. (Japan)
H. Okuni, Toshiba Corp. (Japan)
M. Hosoya, Toshiba Corp. (Japan)
A. Sai, Toshiba Corp. (Japan)
J. Matsuno, Toshiba Corp. (Japan)
S. Saigusa, Toshiba Corp. (Japan)
T. Itakura, Toshiba Corp. (Japan)

Published in SPIE Proceedings Vol. 8985:
Terahertz, RF, Millimeter, and Submillimeter-Wave Technology and Applications VII
Laurence P. Sadwick; Créidhe M. O'Sullivan, Editor(s)

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