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Proceedings Paper

Influences of temperature and etching voltage on the surface morphology of photo-electro-chemical etching for silicon microchannel arrays
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Paper Abstract

The application fields of high aspect ratio Si microchannel arrays have increased considerably, for example, Si microchannel plates, MEMS devices and so on. By the method of photo-electrochemical etching (PEC), Si microchannel arrays are prepared using n-Si wafer covered by anti-corrosion layers and initiation array pits. The dark current intensity curve of an n-type silicon wafer was presented in aqueous HF. The relationship among temperature, etching voltage and carrier transportation was presented. The influences of temperature and etching voltage on the surface morphology of silicon microchannel arrays were researched. The perfect Si microchannel arrays structure with the pore depth of 297 μm, the pore size of 3 μm and the aspect ratio of 99 was obtained by the method of reducing etching voltage gradually.

Paper Details

Date Published: 16 August 2013
PDF: 6 pages
Proc. SPIE 8912, International Symposium on Photoelectronic Detection and Imaging 2013: Low-Light-Level Technology and Applications, 891209 (16 August 2013); doi: 10.1117/12.2031882
Show Author Affiliations
Yao Zhang, Changchun Univ. of Science and Technology (China)
Qingduo Duanmu, Changchun Univ. of Science and Technology (China)
Feng-yuan Yu, Changchun Univ. of Science and Technology (China)
Yong-zhao Liang, Changchun Univ. of Science and Technology (China)
Jin Chai, Changchun Univ. of Science and Technology (China)
Guo-zheng Wang, Changchun Univ. of Science and Technology (China)
Ji-kai Yang, Changchun Univ. of Science and Technology (China)


Published in SPIE Proceedings Vol. 8912:
International Symposium on Photoelectronic Detection and Imaging 2013: Low-Light-Level Technology and Applications
Benkang Chang; Hui Guo, Editor(s)

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