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Proceedings Paper

Resistive shorts characterization in CMOS standard cells for test pattern generation
Author(s): Andrzej Wielgus; Bartosz Potrykus
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Paper Abstract

This paper presents an extended method of CMOS standard cells characterization for defect based voltage testing. Resistance of a short defect is taken into account while considering faulty behavior caused by this defect and finding the test vectors that detect this fault. Finally, all of found vectors are validated to check their effectiveness in fault covering and the optimal test sequence for all detectable faults is constructed. Experimental results for cells from industrial standard cell library are presented.

Paper Details

Date Published: 25 July 2013
PDF: 7 pages
Proc. SPIE 8902, Electron Technology Conference 2013, 89020W (25 July 2013); doi: 10.1117/12.2031300
Show Author Affiliations
Andrzej Wielgus, Warsaw Univ. of Technology (Poland)
Bartosz Potrykus, Warsaw Univ. of Technology (Poland)

Published in SPIE Proceedings Vol. 8902:
Electron Technology Conference 2013
Pawel Szczepanski; Ryszard Kisiel; Ryszard S. Romaniuk, Editor(s)

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