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Proceedings Paper

New generation CMOS 2D imager evaluation and qualification for semiconductor inspection applications
Author(s): Wei Zhou; Darcy Hart
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Paper Abstract

Semiconductor fabrication process defect inspection industry is always driven by inspection resolution and through-put. With fabrication technology node advances to 2X ~1Xnm range, critical macro defect size approaches to typical CMOS camera pixel size range, therefore single pixel defect detection technology becomes more and more essential, which is fundamentally constrained by camera performance. A new evaluation model is presented here to specifically describe the camera performance for semiconductor machine vision applications, especially targeting at low image contrast high speed applications. Current mainline cameras and high-end OEM cameras are evaluated with this model. Camera performances are clearly differentiated among CMOS technology generations and vendors, which will facilitate application driven camera selection and operation optimization. The new challenges for CMOS detectors are discussed for semiconductor inspection applications.

Paper Details

Date Published: 20 September 2013
PDF: 7 pages
Proc. SPIE 8819, Instrumentation, Metrology, and Standards for Nanomanufacturing, Optics, and Semiconductors VII, 881907 (20 September 2013); doi: 10.1117/12.2026963
Show Author Affiliations
Wei Zhou, Rudolph Technologies, Inc. (United States)
Darcy Hart, Rudolph Technologies, Inc. (United States)

Published in SPIE Proceedings Vol. 8819:
Instrumentation, Metrology, and Standards for Nanomanufacturing, Optics, and Semiconductors VII
Michael T. Postek; Ndubuisi George Orji, Editor(s)

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