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Proceedings Paper

In-die mask registration measurement on 28nm-node and beyond
Author(s): Shen Hung Chen; Yung Feng Cheng; Ming Jui Chen
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Paper Abstract

As semiconductor go to smaller node, the critical dimension (CD) of process become more and more small. For lithography, RET (Resolution Enhancement Technology) applications can be used for wafer printing of smaller CD/pitch on 28nm node and beyond. SMO (Source Mask Optimization), DPT (Double Patterning Technology) and SADP (Self-Align Double Patterning) can provide lower k1 value for lithography. In another way, image placement error and overlay control also become more and more important for smaller chip size (advanced node). Mask registration (image placement error) and mask overlay are important factors to affect wafer overlay control/performance especially for DPT or SADP. In traditional method, the designed registration marks (cross type, square type) with larger CD were put into scribe-line of mask frame for registration and overlay measurement. However, these patterns are far way from real patterns. It does not show the registration of real pattern directly and is not a convincing method. In this study, the in-die (in-chip) registration measurement is introduced. We extract the dummy patterns that are close to main pattern from post-OPC (Optical Proximity Correction) gds by our desired rule and choose the patterns that distribute over whole mask uniformly. The convergence test shows 100 points measurement has a reliable result.

Paper Details

Date Published: 9 September 2013
PDF: 8 pages
Proc. SPIE 8880, Photomask Technology 2013, 88801O (9 September 2013); doi: 10.1117/12.2025462
Show Author Affiliations
Shen Hung Chen, United Microelectronic Corp. (Taiwan)
Yung Feng Cheng, United Microelectronic Corp. (Taiwan)
Ming Jui Chen, United Microelectronic Corp. (Taiwan)

Published in SPIE Proceedings Vol. 8880:
Photomask Technology 2013
Thomas B. Faure; Paul W. Ackmann, Editor(s)

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