Proceedings PaperReflectance method for the verification of integrated circuit and masking structures
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The inadequacy of the stuck-at fault model has been well aired and oced1 ,2All studies agree that this model does not reflect the physical failures of real devices,3 principally because such failures do not exhibit a 1:1 mapping onto the logic domain.2 ,' Circuit layouts which are based on stick diagrams do however reflect the physical domain in sufficient detail to enable both structural defects, together with shorts and opens in metallic and non-metallic domains, to be detected and located. The author has proposed the adoption of a novel method which processes information obtained from a scanfling laser beam reflected from a surface profile. Scanning may be of a raster nature over the surface, or follow a suitable path search along layouts. The latter search type has been simulated in PROLOG using breadth-first (BRFS), Euler (ES), and neighbour-first (NFS) searches. It is suggested that by creating and modifying an acquired-knowledge database (AKDB), according to defect occurrence, it is also possible to search those regions where defects may be present in order of decreasing probability. Thus a useful library of the distribution of defect density statistics would be created by virtue of this proposal. In this paper the experimental hardware results presented are based upon reflectance measurements obtained by raster scanning in three different optical modes. In addition results of search simulations and a discussion of the AKDB are included. Such a topological approach to the testing problem offers a test structure for exploitation which is technology independent, fast and is adaptable to parallel processing.