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Proceedings Paper

Design and characterization of a 20 Gbit/s clock recovery circuit
Author(s): Paulo M.P. Monteiro; J. Nuno Matos; Atilio M. S. Gameiro; Jose Ferreira da Rocha
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Paper Abstract

In this communication we report the design of a clock recovery circuit produced for the 20 Gbit/s demonstrator of the RACE 2011 project `TRAVEL' of the European Community. The clock recovery circuit is based on an open loop structure using a dielectric resonator narrow bandpass filter with a high quality factor. A detailed electrical characterization of the circuit and also its sensitivity to temperature and detuning variations are presented. The experimental results show that the circuit is a very attractive solution for the forthcoming STM-128 optical links.

Paper Details

Date Published: 22 February 1995
PDF: 9 pages
Proc. SPIE 2449, Fiber Optic Network Components, (22 February 1995); doi: 10.1117/12.201959
Show Author Affiliations
Paulo M.P. Monteiro, Univ. de Aveiro (Portugal)
J. Nuno Matos, Univ. de Aveiro (Portugal)
Atilio M. S. Gameiro, Univ. de Aveiro (Portugal)
Jose Ferreira da Rocha, Univ. de Aveiro (Portugal)


Published in SPIE Proceedings Vol. 2449:
Fiber Optic Network Components
S. Iraj Najafi; Henri Porte, Editor(s)

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