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Proceedings Paper

High-speed optical correlator with custom electronics interface design
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Paper Abstract

Jet Propulsion Laboratory has developed an innovative Grayscale Optical Correlator (GOC) architecture using a pair of Digital Light Processor Spatial Light Modulator (DLP SLM) as the input and filter devices and a CMOS sensor for correlation output detection [1-5]. In order to achieve ultra high-speed Automatic Target Recognition (ATR), we have developed custom Electronic Interfaces to maximize the system data throughput rate for both the DLP and CMOS. The high-performance Electronic Interface System (EIS) is capable of achieving sustained 1000 frames per second (fps) at 1920x1024 data frame size. In this paper, we will first overview the new GOC architecture. We will the depict the detailed design of the EIS for the DLP SLM and CMOS. The innovation of JPL’s high-performance digital/optical ATR system is in its implementation of a high-speed, high-resolution DLP display, and a high-speed CMOS camera sensor with an advanced I/O interface and high-speed parallel on-board processing capability.

Paper Details

Date Published: 29 April 2013
PDF: 8 pages
Proc. SPIE 8748, Optical Pattern Recognition XXIV, 874803 (29 April 2013); doi: 10.1117/12.2018262
Show Author Affiliations
Tien-Hsin Chao, Jet Propulsion Lab. (United States)
Thomas T. Lu, Jet Propulsion Lab. (United States)


Published in SPIE Proceedings Vol. 8748:
Optical Pattern Recognition XXIV
David Casasent; Tien-Hsin Chao, Editor(s)

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