Share Email Print
cover

Proceedings Paper

Characterization of an asymmetric nonlinear component of process induced distortion in thermally stressed silicon wafers
Author(s): Paul T. Herrington; Bruce E. Woolery
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Process Induced Distortion (PID) was characterized on a Non-thermally Ramped N channel Logic technology. Worst case registration locations were identified by mapping 120 registration sites per wafer on 8 wafers with a Quaestor measuring system. Final characterization of the effects of PD on registration was done by measuring 8 sites per wafer on more than 200 wafers. A thermally ramped process was developed that reduced PD from O. 596um to O. O8Oum for worst case location residual Y component (non-linear component of registration) and from -7 to -2 ppm for the Magnification offset in Y(YMAG a linear component of distortion). Non-Ramped lots processed together exhibited more than twice the residual PID at the Source end vs the Handle end of the Diffusion Furnace load O. 918um to O. 479um respectively. Ramped lots showed no differences in residual PID between Source and Handle ends and measured O. 123um and O. ll6um respectively. Yield and Reliability were improved on the Ramped portion of ten split lots. Die Yields improved due to a reduction in crystal slip several regions were impacted including the areas of the worst case residual PID. Contact Electromigration jeopardy was reduced by an improvement in metal-contact coverage from 60 to 100 for the median die in the worst case registration locations. 1.

Paper Details

Date Published: 1 June 1990
PDF: 7 pages
Proc. SPIE 1264, Optical/Laser Microlithography III, (1 June 1990); doi: 10.1117/12.20179
Show Author Affiliations
Paul T. Herrington, Intel Corp. (United States)
Bruce E. Woolery, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 1264:
Optical/Laser Microlithography III
Victor Pol, Editor(s)

© SPIE. Terms of Use
Back to Top