Share Email Print
cover

Proceedings Paper

Fault tolerant architectures by partial reconfiguration
Author(s): Luis Andrés Cardona; Yi Guo; Carles Ferrer
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

The utilization of SRAM-based FPGAs in the implementation of embedded systems is in continuous growth. The flexibility that these devices offer in terms of hardware re-programming can be also a critical point to take into account when designing fault tolerant systems. As configuration values are stored in volatile memory, any event that affects this configuration memory can lead to undesirable changes in the circuits and as a consequence, erroneous outcomes can be obtained. This paper presents an approach to add fault tolerance in an aerospace application implemented in a commercial-off-the shelf FPGA (Virtex-5). By using this device, the partial reconfiguration facility can be exploited. This feature allows us to get more flexibility in hardware management at run-time also as a mean to correct specific parts of the system when faults are detected. Results regarding influence in area by using different approaches are presented.

Paper Details

Date Published: 28 May 2013
PDF: 7 pages
Proc. SPIE 8764, VLSI Circuits and Systems VI, 87640M (28 May 2013); doi: 10.1117/12.2017594
Show Author Affiliations
Luis Andrés Cardona, Instituto de Microelectrónica de Barcelona (Spain)
Univ. Autònoma de Barcelona (Spain)
Yi Guo, Instituto de Microelectrónica de Barcelona (Spain)
Carles Ferrer, Instituto de Microelectrónica de Barcelona (Spain)
Univ. Autònoma de Barcelona (Spain)


Published in SPIE Proceedings Vol. 8764:
VLSI Circuits and Systems VI
Teresa Riesgo; Massimo Conti, Editor(s)

© SPIE. Terms of Use
Back to Top