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Proceedings Paper

FPGA-based implementation for steganalysis: a JPEG-compatibility algorithm
Author(s): E. Gutierrez-Fernandez; M. Portela-García; C. Lopez-Ongil; M. Garcia-Valderas
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Paper Abstract

Steganalysis is a process to detect hidden data in cover documents, like digital images, videos, audio files, etc. This is the inverse process of steganography, which is the used method to hide secret messages. The widely use of computers and network technologies make digital files very easy-to-use means for storing secret data or transmitting secret messages through the Internet. Depending on the cover medium used to embed the data, there are different steganalysis methods. In case of images, many of the steganalysis and steganographic methods are focused on JPEG image formats, since JPEG is one of the most common formats. One of the main important handicaps of steganalysis methods is the processing speed, since it is usually necessary to process huge amount of data or it can be necessary to process the on-going internet traffic in real-time. In this paper, a JPEG steganalysis system is implemented in an FPGA in order to speed-up the detection process with respect to software-based implementations and to increase the throughput. In particular, the implemented method is the JPEG-compatibility detection algorithm that is based on the fact that when a JPEG image is modified, the resulting image is incompatible with the JPEG compression process.

Paper Details

Date Published: 28 May 2013
PDF: 7 pages
Proc. SPIE 8764, VLSI Circuits and Systems VI, 876407 (28 May 2013); doi: 10.1117/12.2017476
Show Author Affiliations
E. Gutierrez-Fernandez, Univ. Carlos III de Madrid (Spain)
M. Portela-García, Univ. Carlos III de Madrid (Spain)
C. Lopez-Ongil, Univ. Carlos III de Madrid (Spain)
M. Garcia-Valderas, Univ. Carlos III de Madrid (Spain)

Published in SPIE Proceedings Vol. 8764:
VLSI Circuits and Systems VI
Teresa Riesgo; Massimo Conti, Editor(s)

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