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Proceedings Paper

STAR: FPGA-based software defined satellite transponder
Author(s): Daniele Davalle; Riccardo Cassettari; Sergio Saponara; Luca Fanucci; Luca Cucchi; Franco Bigongiari; Walter Errico
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Paper Abstract

This paper presents STAR, a flexible Telemetry, Tracking & Command (TT&C) transponder for Earth Observation (EO) small satellites, developed in collaboration with INTECS and SITAEL companies. With respect to state-of-the-art EO transponders, STAR includes the possibility of scientific data transfer thanks to the 40 Mbps downlink data-rate. This feature represents an important optimization in terms of hardware mass, which is important for EO small satellites. Furthermore, in-flight re-configurability of communication parameters via telecommand is important for in-orbit link optimization, which is especially useful for low orbit satellites where visibility can be as short as few hundreds of seconds. STAR exploits the principles of digital radio to minimize the analog section of the transceiver. 70MHz intermediate frequency (IF) is the interface with an external S/X band radio-frequency front-end. The system is composed of a dedicated configurable high-speed digital signal processing part, the Signal Processor (SP), described in technology-independent VHDL working with a clock frequency of 184.32MHz and a low speed control part, the Control Processor (CP), based on the 32-bit Gaisler LEON3 processor clocked at 32 MHz, with SpaceWire and CAN interfaces. The quantization parameters were fine-tailored to reach a trade-off between hardware complexity and implementation loss which is less than 0.5 dB at BER = 10-5 for the RX chain. The IF ports require 8-bit precision. The system prototype is fitted on the Xilinx Virtex 6 VLX75T-FF484 FPGA of which a space-qualified version has been announced. The total device occupation is 82 %.

Paper Details

Date Published: 28 May 2013
PDF: 6 pages
Proc. SPIE 8764, VLSI Circuits and Systems VI, 87640S (28 May 2013); doi: 10.1117/12.2017070
Show Author Affiliations
Daniele Davalle, Univ. di Pisa (Italy)
Riccardo Cassettari, Univ. di Pisa (Italy)
Sergio Saponara, Univ. di Pisa (Italy)
Luca Fanucci, Univ. di Pisa (Italy)
Luca Cucchi, Intecs S.p.A. (Italy)
Franco Bigongiari, Sitael S.p.A. (Italy)
Walter Errico, Sitael S.p.A. (Italy)


Published in SPIE Proceedings Vol. 8764:
VLSI Circuits and Systems VI
Teresa Riesgo; Massimo Conti, Editor(s)

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