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Proceedings Paper

High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology
Author(s): Jieming Ma; Ka Lok Man; Nan Zhang; Sheng-Uei Guan; Taikyeong Ted. Jeong
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Paper Abstract

Estimating arithmetic is a design paradigm for DSP hardware. By allowing structurally incomplete arithmetic circuits to occasionally perform imprecise calculations, higher performance can be achieved in many different electronic systems. By means of approximate compressor design and bottom-up tree topology, this paper presents a novel approach of implementing high-speed, area-efficient and power-aware multipliers. Experimental results are given to show the applicability and effectiveness of our proposed approach.

Paper Details

Date Published: 13 March 2013
PDF: 9 pages
Proc. SPIE 8784, Fifth International Conference on Machine Vision (ICMV 2012): Algorithms, Pattern Recognition, and Basic Technologies, 87841Z (13 March 2013); doi: 10.1117/12.2014353
Show Author Affiliations
Jieming Ma, Univ. of Liverpool Univ. (United Kingdom)
Ka Lok Man, Xi'an Jiaotong-Liverpool Univ. (China)
Nan Zhang, Xi'an Jiaotong-Liverpool Univ. (China)
Sheng-Uei Guan, Xi'an Jiaotong-Liverpool Univ. (China)
Taikyeong Ted. Jeong, Myongji Univ. (Korea, Republic of)


Published in SPIE Proceedings Vol. 8784:
Fifth International Conference on Machine Vision (ICMV 2012): Algorithms, Pattern Recognition, and Basic Technologies
Yulin Wang; Liansheng Tan; Jianhong Zhou, Editor(s)

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