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Proceedings Paper

Silicon-based phased locked loop (PLL) clock recovery to regenerate 2.5-Gbit/s NRZ data
Author(s): Andrea Pallotta
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Paper Abstract

This paper describes a board-level realization of 2.5 Gb/s clock and data regenerator circuit, where the clock recovery function is implemented by a phase locked loop configuration. In order to use a low cost commercially available voltage controlled oscillator (VCO) a Richman quadricorrelator frequency-difference discriminator has been designed. The resultant frequency and phase locked loop (FPLL), makes possible the frequency acquisition even if the VCO starting frequency were out of the PLL pull-in range. All components used are cheap commercially available silicon devices. Measurements, at 10-9 bit error rate, give an input electrical sensitivity less of 5 mVpp with 223-1 pseudo-random input data stream. The recovered clock jitter is compliant with SONET STM-16.

Paper Details

Date Published: 17 February 1995
PDF: 6 pages
Proc. SPIE 2450, Broadband Networks: Strategies and Technologies, (17 February 1995); doi: 10.1117/12.201314
Show Author Affiliations
Andrea Pallotta, Italtel (Italy)


Published in SPIE Proceedings Vol. 2450:
Broadband Networks: Strategies and Technologies
Robert A. Cryan; P. Nalinaj Fernando; Pierpaolo Ghiggino; John M. Senior, Editor(s)

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