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Proceedings Paper

Novel on chip-interconnection structures for giga-scale integration VLSI ICS
Author(s): Usha Rani Nelakuditi; S. N. Reddy
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Paper Abstract

Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

Paper Details

Date Published: 28 January 2013
PDF: 8 pages
Proc. SPIE 8760, International Conference on Communication and Electronics System Design, 876025 (28 January 2013); doi: 10.1117/12.2012451
Show Author Affiliations
Usha Rani Nelakuditi, Vignan Univ. (India)
S. N. Reddy, Vignan Univ. (India)

Published in SPIE Proceedings Vol. 8760:
International Conference on Communication and Electronics System Design
Vijay Janyani; M. Salim; K. K. Sharma, Editor(s)

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